Field of the Invention
The present invention relates to a lithography apparatus, a lithography system, and a method of manufacturing an article.
Description of the Related Art
In a lithography process as a manufacturing process for a semiconductor device, liquid crystal device, or the like, an exposure apparatus is used, which transfers, via a projection optical system, a reticle (mask) pattern onto a substrate (a wafer or glass plate whose surface is coated with a resist). A lithography process for a semiconductor device has, as a pre-process for an exposure process by an exposure apparatus, a coating process of coating the surface of a substrate with a resist (photoresist), and has, as a post-process, a developing process of developing the substrate onto which a pattern has been transferred. As an apparatus which performs a coating process and a developing process, there is available a coating/developing apparatus called a coater/developer having a coating function (spin coater) of uniformly coating the surface of a substrate with a resist while rotating it at high speed and a developing function.
A substrate conveying mechanism arranged between adjacent apparatuses automatically conveys a substrate between an exposure apparatus and a coating/developing apparatus in order to avoid the cumbersome operation of loading a lot processed in each process and improve throughput while maintaining the chemical properties of a resist. In addition, a scheme of connecting the exposure apparatus to the coating/developing apparatus is called inline connection and is adopted in many lithography systems.
In a lithography process for a semiconductor device, a resist pattern is formed, which serves as a mask when performing etching or impurity implantation. In this case, exposure is performed to overlay a reticle pattern on an underlying pattern while an exposure position is corrected based on the positions of alignment marks formed on a substrate (that is, while performing an alignment process).
In order to improve overlay accuracy, an alignment process may be performed with respect to all the shot regions on a substrate. To apply this technique to a manufacturing process for a semiconductor device, it is necessary to also satisfy the requirement of throughput. Under the circumstance, Japanese Patent Nos. 4419233 and 4905617 have proposed a technique of reducing the number of times of alignment detection on the second and subsequent layers by using initial distortion data representing the formation position distortion of a pattern on the first layer for alignment in pattern exposure on the second and subsequent layers.
In order to further improve the overlay accuracy and the throughput, it is conceivable to manage a correction value (offset) which changes for each substrate in a single lot and reflect each correction value.
When, however, improving overlay accuracy by reflecting an offset on a substrate basis, the offset may not be properly reflected for each substrate, and the overlay accuracy may not be properly maintained. This is because, for example, in a coating/developing apparatus, when a substrate loss occurs and a defect (omission) of a substrate of a lot occurs, inconsistency (substrate shift) occurs in the relationship between an offset on a substrate basis and a processing target substrate. In this case, the overlay accuracy deteriorates on substrates of such a lot, resulting in the necessity of rework.